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Ordering number : ENN8087
SANYO Semiconductors
DATA SHEET
Monolithic Digital IC
LB11696V
Overview
Direct PWM Drive Brushless Motor Predriver IC
The LB11696V is a direct PWM drive predriver IC designed for three-phase power brushless motors. A motor driver circuit with the desired output power (voltage and current) can be implemented by adding discrete transistors in the output circuits. Furthermore, the LB11696V provides a full complement of protection circuits allowing it to easily implement high-reliability drive circuits. This device is optimal for driving all types of large-scale motors such as those used in air conditioners and on-demand water heaters.
Functions and Features
* * * * * * * * * * * Three-phase bipolar drive Direct PWM drive (controlled either by control voltage or PWM variable duty pulse input) Built-in forward/reverse switching circuit Start/stop mode switching circuit (stop mode power saving function) Built-in input amplifier 5 V regulator output (VREG pin) Current limiter circuit (Supports 0.25 V (typical) reference voltage sensing based high-precision detection) Undervoltage protection circuit (The operating voltage can be set with a zener diode) Automatic recovery type constraint protection circuit with protection operating state discrimination output (RD pin) Four types of Hall signal pulse outputs Supports thermistor based thermal protection of the output transistors
Specifications
Absolute Maximum Ratings at Ta = 25C
Parameter Supply voltage 1 Output current LVS pin applied voltage Allowable power dissipation 1 Allowable power dissipation 2 Operating temperature Storage temperature Symbol VCC max IO max LVS max Pd max1 Pd max2 Topr Tstg VCC pin UL, VL, WL, UH, VH, and WH pins LVS pin Independent IC When mounted on a 114.3 x 76.1 x 1.6 mm glass epoxy board Conditions Ratings 18 30 18 0.45 1.05 -20 to +100 -55 to +150 Unit V mA V W W C C
Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications. SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein.
SANYO Electric Co.,Ltd. Semiconductor Company
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
N1504TN (OT) No.8087-1/16
LB11696V
Allowable Operating Ranges at Ta = 25C
Parameter Supply voltage range 1-1 Supply voltage range 1-2 Output current 5 V constant voltage output current HP pin applied voltage HP pin output current RD pin applied voltage RD pin output current Symbol VCC1-1 VCC1-2 IO IREG VHP IHP VRD IRD VCC pin VCC pin, when VCC is shorted to VREG. UL, VL, WL, UH, VH, and WH pins Conditions Ratings 8 to 17 4.5 to 5.5 25 -30 0 to 17 0 to 15 0 to 17 0 to 15 Unit V V mA mA V mA V mA
Electrical Characteristics at Ta = 25C, VCC = 12 V
Parameter Current drain 1 Current drain 2 [5 V Constant Voltage Output (VREG pin)] Output voltage Line regulation Load regulation Temperature coefficient [Output Block] Output voltage 1-1 Output voltage 1-2 Output voltage 2 Output leakage current [Hall Amplifier Block] Input bias current Common-mode input voltage range 1 Common-mode input voltage range 2 Hall Input Sensitivity Hysteresis Input voltage low high Input voltage high low [CTL Amplifier] Input offset voltage Input bias current Common-mode input voltage range High-level output voltage Low-level output voltage Open-loop gain [PWM Oscillator (PWM pin)] High-level output voltage Low-level output voltage External capacitor charge current Oscillator frequency Amplitude [TOC pin] Input voltage 1 Input voltage 2 Input voltage 1 low Input voltage 2 low Input voltage 1 high Input voltage 2 high [HP Pin] Output saturation voltage Output leakage current VHPL IHPleak IO = 10 mA VO = 18 V 0.2 0.5 10 V A VTOC1 VTOC2 VTOC1L VTOC2L VTOC1H VTOC2H Output duty: 100% Output duty: 0% Design target value, when VREG = 4.7 V, 100% Design target value, when VREG = 4.7 V, 0% Design target value, when VREG = 5.3 V, 100% Design target value, when VREG = 5.3 V, 0% 2.68 1.2 2.68 1.23 3.02 1.37 3.0 1.35 2.82 1.29 3.18 1.44 3.34 1.5 2.96 1.34 3.34 1.50 V V V V V V VOH (PWM) VOL (PWM) ICHG f (PWM) V (PWM) VPWM = 2.1 V C = 2000 pF 1.4 2.75 1.2 -120 3.0 1.35 -90 22 1.6 1.9 3.25 1.5 -65 V V A kHz Vp-p VIO (CTL) IB (CTL) VICM VOH (CTL) VOL (CTL) G (CTL) ITOC = -0.2 mA ITOC = 0.2 mA f (CTL) = 1 kHz 45 -10 -1 0 VREG - 1.2 VREG - 0.8 0.8 51 1.05 10 1 VREG - 1.7 mV A V V V dB VIN (HA) VSLH (HA) VSHL (HA) IHB (HA) VICM1 VICM2 When a Hall effect device is used Single-sided input bias mode (when a Hall IC is used) -2 0.5 0 80 15 5 -20 24 12 -12 40 20 -5 -0.5 VCC - 2.0 VCC A V V mVp-p mV mV mV VOUT1-1 VOUT1-2 VOUT2 IOleak Low level, IO = 400 A Low level, IO = 10 mA High level, IO = -20 mA 0.2 0.9 VCC - 1.1 VCC - 0.9 10 0.5 1.2 V V V A VREG VREG1 VREG2 VREG3 VCC = 8 to 17 V IO = -5 to -20 mA Design target value 4.7 5.0 40 10 0 5.3 100 30 V mV mV mV/C Symbol ICC1 ICC2 Stop mode Conditions Ratings min typ 12 2.5 max 16 4 Unit mA mA
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No.8087-2/16
LB11696V
Continued from preceding page.
Parameter [CSD Oscillator (CSD pin)] High-level output voltage Low-level output voltage External capacitor charge current External capacitor discharge current Charge/discharge current ratio [RD Pin] Low-level output voltage Output leakage current [Current Limiter Circuit (RF pin)] Limiter voltage [Undervoltage Protection Circuit (LVS pin)] Operating voltage Release voltage Hysteresis [PWMIN Pin] Input frequency High-level input voltage Low-level input voltage Input open voltage Hysteresis High-level input current Low-level input current [S/S Pin] High-level input voltage Low-level input voltage Hysteresis High-level input current Low-level input current [F/R Pin] High-level input voltage Low-level input voltage Input open voltage Hysteresis High-level input current Low-level input current [N1 Pin] High-level input voltage Low-level input voltage Input open voltage High-level input current Low-level input current [N2 Pin] High-level input voltage Low-level input voltage Input open voltage High-level input current Low-level input current VIH (N2) VIL (N2) VIO (N2) IIH (N2) IIL (N2) VN2 = VREG VN2 = 0 V 2.0 0 VREG - 0.5 -10 -130 0 -100 VREG 1.0 VREG +10 V V V A A VIH (N1) VIL (N1) VIO (N1) IIH (N1) IIL (N1) VN1 = VREG VN1 = 0 V 2.0 0 VREG - 0.5 -10 -130 0 -100 VREG 1.0 VREG +10 V V V A A VIH (FR) VIL (FR) VIO (FR) VIS (FR) IIH (FR) IIL (FR) VF/R = VREG VF/R = 0 V 2.0 0 VREG - 0.5 0.2 -10 -130 0.25 0 -90 VREG 1.0 VREG 0.4 +10 V V V V A A VIH (SS) VIL (SS) VIS (SS) IIH (SS) IIL (SS) VS/S = VREG VS/S = 0 V 2.0 0 0.2 -10 -10 0.25 0 -1 VREG 1.0 0.4 +10 V V V A A f (PI) VIH (PI) VIL (PI) VIO (PI) VIS (PI) IIH (PI) IIL (PI) VPWMIN = VREG VPWMIN = 0 V 2.0 0 VREG - 0.5 0.2 -10 -130 0.25 0 -90 50 VREG 1.0 VREG 0.4 +10 kHz V V V V A A VSDL VSDH VSD 3.5 3.95 0.3 3.7 4.15 0.45 3.9 4.35 0.6 V V V VRF RF-RFGND 0.225 0.25 0.275 V VRDL IL (RD) IO = 10 mA VO = 18 V 0.2 0.5 10 V A VOH (CSD) VOL (CSD) ICHG1 ICHG2 RCSD VCSD = 2 V VCSD = 2 V (Charge current)/(discharge current) 2.7 0.7 -3.15 0.1 15 3.0 1.0 -2.5 0.14 18 3.3 1.3 -1.85 0.18 21 V V A A times Symbol Conditions Ratings min typ max Unit
No.8087-3/16
LB11696V
Three-Phase Logic Truth Table ("IN = `H'" indicates the state where IN+ > IN-.)
F/R = L IN1 1 2 3 4 5 6 H H H L L L IN2 L L H H H L IN3 H L L L H H IN1 L L L H H H F/R = H IN2 H H L L L H IN3 L H H H L L PWM VH WH WH UH UH VH Output -- UL UL VL VL WL WL
S/S Pin
Input state H L State Stop Start
PWMIN Pin
Input state High or open L State Output off Output on
N1 and N2 Pins
Input state N1 pin L L High or open High or open N2 pin L High or open L High or open HP output Single Hall sensor period divided by 2 Single Hall sensor period Three Hall sensor synthesized period divided by 2 Three Hall sensor synthesized period
Since the S/S pin does not have an internal pull-up resistor, an external pull-up resistor or equivalent is required to set the IC to the stop state. If either the S/S or PWMIN pins are not used, the unused pin input must be set to the low-level voltage. The HP output can be selected (by the N1 and N2 settings) to be one of the following four functions: the IN1 Hall input converted to a pulse output (one-Hall output), the one-Hall output divided by two, the three-phase output synthesized from the Hall inputs (three-Hall synthesized output) or the three-Hall synthesized output divided by two. Package Dimensions
unit : mm 3191A
Pd max -- Ta
1.2
30
16
Allowable power dissipation, Pdmax -- W
1.05 1
114.3mm x 76.1mm x 1.6mm glass epoxy board
5.6
0.5
7.6
0.8
0.6 0.45 0.4
(1.3) 1.5max
1
9.75
15
0.15
Independent 0.42
0.1
0.22
0.65
(0.33)
0.2
0.18
0 20 40 60 80 100 120
SANYO : SSOP30 (275mil)
0 -20
Ambient temperature, Ta -- C
No.8087-4/16
LB11696V
Pin Assignment
VCC VREG LVS 30 29 28 N2 27 N1 26 HP 25 F/R PWMIN S/S 24 23 22 CSD 21 RD 20 PWM TOC 19 18 EI- 17 EI+ 16
LB11696V
1
2
3
4 WH
5 WL
6 VH
7 VL
8 UH
9 UL
10 IN1-
11
12
13
14
15 IN3+
GND RFGND RF
IN1+ IN2-
IN2+ IN3-
Top view
Pin Functions
Pin No. 1 Symbol GND Ground Pin Description Equivalent circuit
VREG
2
RF GND
Output current detection reference Connect the ground terminal of the external resistor RF to this pin.
2
VREG
3
RF
Output current detection Connect a resistor with a small value between this pin and RFGND. This sets the maximum output current IOUT to be 0.25/Rf.
3
VCC
4 6 8 5 7 9 WH VH UH WL VL UL
Outputs (External transistor drive outputs) The duty control applies to the UH, VH, and WH pins.
4 50 k 5
6 7
8 9
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No.8087-5/16
LB11696V
Continued from preceding page.
Pin No. Pin Name Pin Description Equivalent circuit
VCC
10 11 12 13 14 15
IN1- IN1+ IN2- IN2+ IN3- IN3+
Hall sensor inputs A high-level state is recognized when IN+ > IN-, and a low-level state is recognized under the reverse condition. If noise on the Hall sensor signals becomes a problem, insert capacitors between the IN+ and IN- inputs.
300 11 13 15
300
10 12 14
VCC
16 17
EI+ EI-
Control amplifier inputs The PWMIN pin must be held at the low level for control using this pin to function.
300 17
300
16
VREG
18
TOC
Control amplifier output When the TOC pin voltage rises, the IC changes the UH, VH, and WH output signal PWM duty to increase the torque output.
300
18
40 k
VREG
19
PWM
Shared function pin: PWM oscillator frequency setting and initial reset pulse generation Insert a capacitor between this pin and ground. A capacitor of 2000 pF sets a frequency of about 22 kHz.
200 2 k
19
VREG
20
RD
Motor constraint detection output This pin output is on when the motor is turning and off when the constraint protection circuit operates.
20
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No.8087-6/16
LB11696V
Continued from preceding page.
Pin No. Pin Name Pin Description Equivalent circuit
VREG
21
CSD
Constraint protection circuit operating time setting Insert a capacitor between this pin and ground. This pin must be connected to ground if the constraint protection circuit is not used.
300
21
VREG
22
S/S
Start/Stop input A low-level input sets the IC to start mode, and a highlevel input sets it to stop mode.
3.5 k
22
VREG
23
PWM IN
PWM pulse input A low-level input specifies the output drive state, and a high-level or open input specifies the output off state. When this pin is used for control, the TOC pin voltage must be set to a control amplifier input that results in a 100% duty.
50 k 3.5 k
23
VREG
50 k
24 F/R Forward/reverse input
3.5 k
24
VREG
25
HP
Hall signal output (This is an open-collector output) One of four output types is selected by the N1 and N2 pin settings.
25
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No.8087-7/16
LB11696V
Continued from preceding page.
Pin No. Pin Name Pin Description Equivalent circuit
VREG
50 k
26
N1
Hall signal output (HP signal) type selector
300
26
VREG
50 k
27 N2 Hall signal output (HP signal) type selector
300
27
VCC 28
Undervoltage protection voltage detection If a 5 V or higher supply voltage is to be detected, set the detection voltage by inserting an appropriate zener diode in series.
28
LVS
VCC
29
VREG
Stabilized power supply output (5 V output) Insert a capacitor (about 0.1 F) between this pin and ground for stabilization.
29
30
VCC
Power supply. Insert a capacitor between this pin and ground for stabilization.
No.8087-8/16
LB11696V
Hall Sensor Signal Input/Output Timing Chart
F/R = L IN1
IN2
IN3
UH VH WH UL VL WL
F/R = H IN1
IN2
IN3
UH VH WH UL VL WL
Areas shown in gray (
) indicate PWM output.
No.8087-9/16
VREG 5V RD CSD VM
TOC LVS LVSD
Application Circuit Examples
EI-
- RD
CTL VREG COMP VCC VREG
EI+
+
CSD OSC
PWM
PWM OSC
PWMIN CONTROL LOGIC PRI DRIVER HP LOGIC HALL LOGIC HALL F/R N1 N2 HYS AMP CURR LIM
PWM IN
UH UL VH VL WH WL
LB11696V
Bipolar transistor drive (high side PWM) using a 5 V power supply
VREG
HP
VREF
S/S
RF RFGND
VREG N1 N2
S/S
F/R
IN1+ IN1- IN2+ IN2- IN3+ IN3-
GND
VCC
No.8087-10/16
VREG
RD CSD 12 V LVS LVSD
TOC - RD + VREG PWM OSC VCC COMP VREG
VM
EI-
CSD OSC
CTL
EI+
PWM
PWMIN PWM IN
CONTROL LOGIC PRI DRIVER HP LOGIC HALL LOGIC HALL
UL UH VL VH WL WH
MOS transistor drive (low side PWM) using a 12 V power supply
LB11696V
VREG
HP VREF
S/S F/R N1 N2
HYS AMP
CURR LIM GND
RF
RFGND S/S N1 N2 F/R IN1+ IN1- IN2+ IN2- IN3+ IN3-
VREG
VCC
No.8087-11/16
VREG
RD 12 V LVS LVSD
CSD VM
TOC
EI-
- RD
EI+ VREG COMP VCC VREG
+
CSD OSC
PWM
PWM OSC
Variable duty PWMIN pulse input CONTROL LOGIC PRI DRIVER HP LOGIC HALL LOGIC HALL F/R N1 N2 HYS AMP CURR LIM F/R N1 N2 IN1+ IN1- IN2+ IN2- IN3+ IN3-
PWM IN
UL UH VL VH WL WH RF
LB11696V
VREG
HP
VREF
S/S
VREG
S/S
GND RFGND
Thermistor
VCC
NMOS transistor + PNP transistor drive (low side PWM) using a 12 V power supply with thermal protection implemented using a thermistor
No.8087-12/16
LB11696V
LB11696V Functional Description 1. Output Drive Circuit The LB11696V adopts direct PWM drive to minimize power loss in the outputs. The output transistors are always saturated when on, and the motor drive power is adjusted by changing the on duty of the output. The output PWM switching is performed on the UH, VH, and WH outputs. Since the UL to WL and UH to WH outputs have the same output form, applications can select either low side PWM or high side PWM drive by changing the way the external output transistors are connected. Since the reverse recovery time of the diodes connected to the non-PWM side of the outputs is a problem, these devices must be selected with care. (This is because through currents will flow at the instant the PWM side transistors turn on if diodes with a short reverse recovery time are not used.) 2. Current Limiter Circuit The current limiter circuit limits the output current peak value to a level determined by the equation I = VFR/Rf (VRF = 0.25 V typical, Rf: To the RF pin Current current detection resistor). This circuit suppresses the output current by detection reducing the output on duty. resistor High-precision detection can be implemented by connecting the lines from the RF and RFGND pins close to the two terminal of the current detection resistor Rf. The current limiter circuit includes an internal filter circuit to prevent incorrect current limiter circuit operation due to detecting the output diode reverse recovery current due to PWM operation. Although there should be no problems with the internal filter circuit in normal applications, applications should add an external filter circuit (such as an RC low-pass filter) if incorrect operation occurs (if the diode reverse recovery current flows for longer than 1 s). 3. Power Saving Circuit This IC goes to a low-power mode (power saving state) when set to the stop state with the S/S pin. In the power saving state, the bias currents in most of the circuits are cut off. However, the 5 V regulator output (VREG) is still provided in the power saving state. If it is also necessary to cut the Hall device bias current, this function can be provided by an application that, for example, connects the Hall devices to 5 V through PNP transistors.
To the VREG pin
To the S/S pin
Hall device
4. Notes on the PWM Frequency The PWM frequency is determined by the capacitor C (F) connected to the PWM pin. fPWM 1/(22500 x C) If a 2000 pF capacitor is used, the circuit will oscillate at about 22 kHz. If the PWM frequency is too low, switching noise will be audible from the motor, and if it is too high, the output power loss will increase. Thus a frequency in the range 15 to 50 kHz must be used. The capacitor's ground terminal must be placed as close as possible to the IC's ground pin to minimize the influence of output noise and other noise sources. 5. Control Methods The output duty can be controlled by either of the following methods * Control based on comparing the TOC pin voltage to the PWM oscillator waveform The low side output transistor duty is determined according to the result of comparing the TOC pin voltage to the PWM oscillator waveform. When the TOC pin voltage is 1.35 V or lower, the duty will be 0%, and when it is 3.0 V or higher, the duty will be 100%. Since the TOC pin is the output of the control amplifier (CTL), a control voltage cannot be directly input to the TOC pin. Normally, the control amplifier is used as a full feedback amplifier (with the EI- pin connected to the TOC pin) and a DC voltage is input to the EI+ pin (the EI+ pin voltage will become equal to the TOC pin voltage). When the EI+ pin voltage becomes higher, the output duty increases. Since the motor will be driven when the EI+ pin is in the open state, a pull-down resistor must be connected to the EI+ pin if the motor should not operate when EI+ is open. When TOC pin voltage control is used, a low-level input must be applied to the PWMIN pin or that pin connected to ground.
No.8087-13/16
LB11696V
* Pulse Control Using the PWMIN Pin A pulse signal can be input to the PWMIN pin, and the output can be controlled based on the duty of that signal. Note that the output is on when a low level is input to the PWMIN pin, and off when a high level is input. When the PWMIN pin is open it goes to the high level and the output is turned off. If inverted input logic is required, this can be implemented with an external transistor (npn). When controlling motor operation from the PWMIN pin, the EI- pin must be connected to ground, and the EI+ pin must be connected to the TOC pin. Note that since the PWM oscillator is also used as the clock for internal circuits, a capacitor (about 2000 pF) must be connected to the PWM pin even if the PWMIN pin is used for motor control. 6. Hall Input Signals A signal input with an amplitude in excess of the hysteresis (80 mV maximum) is required for the Hall inputs. Considering the possibility of noise and phase displacement, an even larger amplitude is desirable. If disruptions to the output waveforms (during phase switching) or to the HP output (Hall signal output) occur due to noise, this must be prevented by inserting capacitors across the inputs. The constraint protection circuit uses the Hall inputs to discriminate the motor constraint state. Although the circuit is designed to tolerate a certain amount of noise, care is required when using the constraint protection circuit. If all three phases of the Hall input signal system go to the same input state, the outputs are all set to the off state (the UL, VL, WL, UH, VH, and WH outputs all go to the low level). If the outputs from a Hall IC are used, fixing one side of the inputs (either the + or - side) at a voltage within the common-mode input voltage range allows the other input side to be used as an input over the 0 V to VCC range. 7. Undervoltage Protection Circuit The undervoltage protection circuit turns one side of the outputs (UH, VH, and WH) off when the LVS pin voltage falls below the minimum operation voltage (see the Electrical Characteristics). To prevent this circuit from repeatedly turning the outputs on and off in the vicinity of the protection To the power operating voltage, this circuit is designed with hysteresis. Thus the output supply detected will not recover until the operating voltage rises 0.45 V (typical). The protection operating voltage detection level is set up for 5 V systems. To the LVS pin The detected voltage level can be increased by shifting the voltage by inserting a zener diode in series with the LVS pin to shift the detection level. The LVS influx current during detection is about 75 A. To increase the diode current to stabilize the zener diode voltage rise, insert a resistor between the LVS pin and ground. If the LVS pin is left open, the internal pull-down resistor will result in the IC seeing a ground level input, and the output will be turned off. Therefore, a voltage in excess of the LVS circuit clear voltage (about 4.35 V) must be applied to the LVS pin if the application does not use the undervoltage protection circuit. The maximum rating for the LVS pin applied voltage is 18 V. 8. Constraint Protection Circuit When the motor is physically constrained (held stopped), the CSD pin external capacitor is charged (to about 3.0 V) by a constant current of about 2.5 A and is then discharged (to about 1.0 V) by a constant current of about 0.14 A. This process is repeated, generating a sawtooth waveform. The constraint protection circuit turns motor drive on and off repeatedly based on this sawtooth waveform. (The UH, VH, and WH side outputs are turned on and off.) Motor drive is on during the period the CSD pin external capacitor is being charged from about 1.0 V to about 3.0 V, and motor drive is off during the period the CSD pin external capacitor is being discharged from about 3.0 V to about 1.0 V. The IC and the motor are protected by this repeated drive on/off operation when the motor is physically constrained. The motor drive on and off times are determined by the value of the connected capacitor C (in F). TCSD1 (drive on period) 0.8 x C (seconds) TCSD2 (drive off period) 14.3 x C (seconds) When a 0.47 F capacitor is connected externally to the CSD pin, this iterated operation will have a drive on period of about 0.38 seconds and a drive off period of about 6.7 seconds.
No.8087-14/16
LB11696V
While the motor is turning, the discharge pulse signal (generated once for each Hall input period) that is created by combining the Hall inputs internally in the IC discharges the CSD pin external capacitor. Since the CSD pin voltage does not rise, the constraint protection circuit does not operate. When the motor is physically constrained, the Hall inputs do not change and the discharge pulses are not generated. As a result, the CSD pin external capacitor is charged by a constant current of 2.5 A to about 3.0 V, at which point the constraint protection circuit operates. When the constraint on the motor is released, the constraint protection function is released. Connect the CSD pin to ground if the constraint protection circuit is not used. 9. Forward/Reverse Direction Switching This IC is designed so that through currents (due to the output transistor off delay time when switching) do not flow in the output when switching directions when the motor is turning. However, if the direction is switched when the motor is turning, current levels in excess of the current limiter value may flow in the output transistors due to the motor coil resistance and the motor back EMF state when switching. Therefore, designers must consider selecting external output transistors that are not destroyed by those current levels or only switching directions after the speed has fallen below a certain speed. 10. Handling Different Power Supply Types When this IC is operated from an externally supplied 5 V power supply (4.5 to 5.5 V), short the VCC pin to the VREG pin and connect them to the external power supply. When this IC is operated from an externally supplied 12 V power supply (8 to 17 V), connect the VCC pin to the power supply. (The VREG pin will generate a 5 V level to function as the control circuit power supply.) 11. Power Supply Stabilization Since this IC uses a switching drive technique, the power supply line level can be disturbed easily. Therefore capacitors with adequate capacitance to stabilize the power supply line must be inserted between VCC and ground. If diodes are inserted in the power supply lines to prevent destruction if the power supply is connected with reverse polarity, the power supply lines are even more easily disrupted, and even larger capacitors are required. If the power supply is turned on and off by a switch, and if there is a significant distance between that switch and the stabilization capacitor, the supply voltage can be disrupted significantly by the line inductance and surge current into the capacitor. As a result, the withstand voltage of the device may be exceeded. In application such as this, the surge current must be suppressed and the voltage rise prevented by not using ceramic capacitors with a low series impedance, and by using electrolytic capacitors instead. 12. VREG Stabilization To stabilize the VREG voltage, which is the control circuit power supply, a 0.1 F or larger capacitor must be inserted between the VREG pin and ground. The ground side of this capacitor must connected to the IC ground pin with a line that is as short as possible.
No.8087-15/16
LB11696V
Specifications of any and all SANYO products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO products(including technical data,services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be expor ted without obtaining the expor t license from the author ities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Electric Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only ; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of November, 2004. Specifications and information herein are subject to change without notice.
PS No.8087-16/16

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